Optical sensors to be contained in portable equipment have been under desires for higher sensitivity and higher accuracy.
In manufacture of such optical sensors, variations in light-reception sensitivity or characteristic variations in light-emission intensity have been at issue. As a result, there is a need for providing the semiconductor integrated circuit forming an optical sensor with a fuse-containing trimming circuit and adjusting the semiconductor integrated circuit by melt-and-cut of fuses so as to reduce the manufacturing variations of the optical sensor. In this case, since the melt-and-cut of the fuses causes the semiconductor integrated circuit to be damaged, the number of fuses to be melted and cut is desirably as small as possible.
As such a semiconductor integrated circuit including the fuse-containing trimming circuit as shown above, a semiconductor integrated circuit device is disclosed in JP S63-164239 A. This semiconductor integrated circuit device, as shown in FIG. 8, includes an analog circuit 3, which is a circuit to be corrected, a first trimming circuit 1 for correcting a circuit constant of the analog circuit 3 in an increasing-direction, and a second trimming circuit 2 for correcting a circuit constant of the analog circuit 3 in a decreasing-direction. The first trimming circuit 1 has resistors R1, R2, R3 having weighted resistance values R, 2R, 4R, respectively, while the second trimming circuit 2 has resistors R4, R5, R6 having weighted resistance values R, 2R, 4R, respectively.
The resistors R1-R6 are connected to fuse elements F1-F6 serving as storage elements via switching elements (transistors) Q1-Q6 and inverters, respectively, where programming (writing) onto the individual fuse elements F1-F6 is achieved by applying a specified program voltage to a terminal pad P.
That is, fuse elements to which the program voltage is applied from the terminal pad P are melted and cut to go OFF state, and resistors corresponding to the melt-and-cut only are disconnected from the analog circuit 3. In contrast to this, non-melted-and-cut resistors are connected in parallel to an emitter load resistor RE of the analog circuit 3. Thus, resistors to be disconnected are selected by the programming to correct the circuit constant of the analog circuit 3.
Also, as a semiconductor integrated circuit including a trimming information generation circuit for detecting information as to fuses melted and cut by the trimming circuit to generate and output trimming information, a semiconductor integrated circuit device is disclosed in JP 2008-293206 A. This semiconductor integrated circuit device, as shown in FIG. 9, includes a trimming signal generation circuit 6 and a variable resistor element 7.
The trimming signal generation circuit 6 detects melt-and-cut information on the built-in fuses to output it as trimming information.
In the variable resistor element 7, series-connected five resistors R0-R4 are provided, and the individual resistors R0, R1, R2, R3, R4 have weighted resistance values R, R, 2R, 4R, 8R, respectively. Further, source and drain of a transistor MN0 serving as a switching element is connected to both ends of the resistor R1. For the rest, similarly, source and drain of a transistor MN1 are connected to both ends of the resistor R2, source and drain of a transistor MN2 are connected to both ends of the resistor R3, and source and drain of a transistor MN3 are connected to both ends of the resistor R4.
Also, a trimming signal terminal FUSE[0] of the trimming signal generation circuit 6 is connected to gate of the transistor MN0. For the rest, similarly, a trimming signal terminal FUSE[1] is connected to gate of the transistor MN1, a trimming signal terminal FUSE[2] is connected to gate of the transistor MN2, and a trimming signal terminal FUSE[3] is connected to gate of the transistor MN3.
As described before, the number of fuses to be melted and cut for adjustment of the semiconductor integrated circuit device 5 is desirably as small as possible and, for this purpose, the number itself of fuses required for the adjustment is desirably small as well. As a trimming signal generation circuit 6 in which the fuses for adjustment are lessened in number as described above, a circuit construction as shown in FIG. 10 is conceivable.
In the trimming signal generation circuit 6 shown in FIG. 10, internal circuits 6a-6d are provided for individual trimming signal terminals FUSE[0]-FUSE[3], respectively, and one fuse is provided for each one of the internal circuits 6a-6d, correspondingly. Then, in the internal circuit 6a, a node N0 connected to the trimming signal terminal FUSE[0] is connected to a power supply Vcc via a pull-up resistor RB0 and moreover grounded via a fuse F0. Similarly also in the internal circuits 6b-6d, the trimming signal terminal FUSE[1] is connected to a power supply Vcc via a pull-up resistor RB1 and moreover grounded via a fuse F1, the trimming signal terminal FUSE[2] is connected to a power supply Vcc via a pull-up resistor RB2 and moreover grounded via a fuse F2, and the trimming signal terminal FUSE[3] is connected to a power supply Vcc via a pull-up resistor RB3 and moreover grounded via a fuse F3.
In the semiconductor integrated circuit device 5 of the above-described construction, for example, when the fuse F2 of the internal circuit 6c is melted and cut, a trimming signal of a voltage close to the power supply voltage Vcc is outputted from the corresponding trimming signal terminal FUSE[2]. Then, the transistor MN2 of the variable resistor element 7 is turned on, so that both ends of the resistor R3 are short-circuited. Meanwhile, on condition that the fuse F1 of the internal circuit 6b is not melted and cut, the corresponding trimming signal terminal FUSE[1] remains grounded. Then, the transistor MN1 of the variable resistor element 7 keeps in the OFF state, so that both ends of the resistor R2 are not short-circuited. Thus, transistors corresponding to melted-and-cut fuses are turned on, so that both ends of the corresponding resistors are short-circuited. As a result, a combined resistance value of the series-connected resistors R0-R4 is a total value of resistance values of the resistors corresponding to the non-melted-and-cut fuses.
FIGS. 11A-11E show: trimming information which is formed of a 4-bit bit string (least significant bit corresponds to trimming signal terminal FUSE[0]) representing four trimming signals simultaneously outputted from the trimming signal terminals FUSE[0]-FUSE[3] to select resistors that are short-circuited and nullified from the array of resistors R1-R4 in the variable resistor element 7 (FIG. 11A); resistor selection information which is formed of a 4-bit bit string (least significant bit corresponds to transistor MN0) representing four resistor selection signals simultaneously inputted to the gates of the transistors MN0-MN3 (FIG. 11B); combined resistance values of the resistors R0-R4 (FIG. 11C); numbers of melted-and-cut fuses (FIG. 11D); and an appearance frequency distribution (hereinafter, referred to simply as distribution from time to time) of a certain characteristic value of the obtained semiconductor integrated circuit device 5 (FIG. 11E).
Herein, in the trimming information, a ‘1’ stands for a trimming signal of level ‘H,’ i.e. for a melted-and-cut fuse, while a ‘0’ stands for a trimming signal of level ‘L,’ i.e. for a non-melted-and-cut fuse. Further, in the resistor selection information, a ‘1’ stands for a resistor selection signal of level ‘H,’ i.e. for turn-on of a transistor, while a ‘0’ stands for a resistor selection signal of level ‘L,’ i.e. for turn-off of a transistor.
As shown in FIGS. 11A-11E, in a range of “mean value±2σ (standard deviation)” under which do fall most (95.45%) of manufacturing variations of manufactured semiconductor integrated circuit devices 5, a total number of melted-and-cut fuses equals 10. It is noted that the number of melted-and-cut fuses is a number of ‘1’s in corresponding trimming information.
However, the prior-art semiconductor integrated circuit device 5 shown above has problems as shown below.
That is, the melt-and-cut of fuses causes the semiconductor to be damaged to a considerable extent. Also, there is a fear for occurrence of a problem in reliability of the melt-and-cut, giving adverse effects on the quality. Therefore, the number of melted-and-cut fuses is desirably lessened to the least possible.
In FIGS. 11A-11E, in the manufacturing-variation range of “mean value±2σ (standard deviation),” the number of melted-and-cut fuses per one piece of trimming information is 1 to 3 fuses, which seems smaller numbers at a glance. However, since most (95.45%) of manufacturing variations fall within the manufacturing-variation range of “mean value±2σ (standard deviation),” actually melted-and-cut fuses count a large total number, so that the probability of adverse effects exerted on quality becomes higher correspondingly.
Such a problem similarly matters also in the case of the semiconductor integrated circuit device disclosed in JP S63-164239 A. In addition, as shown in FIG. 8, a program to be inputted to each of the fuse elements F1-F6 is in six bits, which is larger than the four bits of the semiconductor integrated circuit device 5 shown in FIG. 9, the number of melted-and-cut fuses falling within the manufacturing-variation range of “mean value±2σ (standard deviation)” becomes larger to an extent corresponding to the bit difference.